Partial Reconfiguration Fpga Thesis

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For the purposes of this thesis we chose four cryptographic modules (AES128, AES192, AES256 and SHA3-512).

Firstly, we made all the appropriate modifications needed to utilize thecryptographic modules in the So C and designed the appropriate AXI4-Stream compliant interfaces toenable communication between the peripherals and the processor, with respective compromises to thedifferent modules’ architecture, the processing system’s limitations and PR’s restrictions.

It is found that a No C provides much better performance than a single channel bus and similar performance to a multi-channel bus in both parallel and parallel-pipelined FFT systems.

This suggests that a No C is a better choice for systems with multiple simultaneous communications like the FFT.

Partial Reconfiguration (PR) takes this flexibilityone step further, by allowing an operating FPGA design to modify a part of itself, while the rest of thesystem continues to function normally, without compromising the integrity of the computation runningon those parts of the device that are not being reconfigured.

This technique leads to reduction of theamount of resources required to implement a given function, with consequent reductions in cost andpower consumption, provides flexibility in the algorithms/protocols available to an application andaccelerates computing by enabling a design to be ready to correspond to new computationrequirements much faster.While partial reconfiguration can offer many benefits, it is still rarely exploited in practical applications.Few full realizations of partially reconfigurable systems in current FPGA technologies have been published.These two interconnect schemes are implemented and evaluated in terms of performance, area and power consumption using FFT (Fast Fourier Transform) and ANN(Artificial Neural Network) systems as benchmarks.Conclusions drawn from these results include recommendations concerning the interconnect approach for different kinds of applications.More application experiments are required to understand the benefits and limitations of implementing partially reconfigurable systems and to guide their further development.The motivation of this thesis is to fill this research gap by providing empirical evidence of the cost and benefits of different interconnect architectures.Results from the experiments with dynamic partial reconfiguration demonstrate that buses have the advantages of better resource utilization and smaller reconfiguration time and memory than No Cs. They have the advantage of placing almost all of the communication infrastructure in the dynamic reconfiguration region.This means that different applications running on the FPGA can use different interconnection strategies without the overhead of fixed bus resources in the static region.Bus-based interconnect achieves better performance and consume less area and power than No Cbased scheme for the fully-connected feed-forward NN system.This suggests buses are a better choice for systems that do not require many simultaneous communications or systems with broadcast communications like a fully-connected feed-forward NN.

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